 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ITF87072DK8T TM Data Sheet March 2000 File Number 4812.3 6A, 20V, 0.037 Ohm, Dual P-Channel, 2.5V Specified Power MOSFET Packaging SO8 (JEDEC MS-012AA) BRANDING DASH Features * Ultra Low On-Resistance - rDS(ON) = 0.037, VGS = -4.5V - rDS(ON) = 0.039, VGS = -4.0V - rDS(ON) = 0.059, VGS = -2.5V * Gate to Source Protection Diode * Simulation Models - Temperature Compensated PSPICETM and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.intersil.com * Peak Current vs Pulse Width Curve * Transient Thermal Impedance Curve vs Board Mounting Area 5 1 2 3 4 Symbol DRAIN1(8) DRAIN1(7) SOURCE1(1) GATE1(2) DRAIN2(6) DRAIN2(5) SOURCE2(3) GATE2(4) * Switching Time vs RGS Curve Ordering Information PART NUMBER ITF87072DK8T PACKAGE SO8 87072 BRAND NOTE: When ordering, use the entire part number. ITF87072DK8T is available only in tape and reel. Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified ITF87072DK8T -20 -20 12 6.0 6.0 1.5 1.5 Figure 4 2.5 20 -55 to 150 300 260 UNITS V V V A A A A W mW/oC oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA = 25oC, VGS = -4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 25oC, VGS = -4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = -4.0V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = -2.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Technical Brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.14 in2 (90.3 mm2) copper pad at 1 second. 3. 228oC/W measured using FR-4 board with 0.006 in2 (3.9 mm2) copper pad at 1000 second. 1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. SABER(c) is a Copyright of Analogy Inc. , PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 ITF87072DK8T Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A Figure 10 ID = 6.0A, VGS = -4.5V Figures 8, 9 ID = 1.5A, VGS = -4.0V Figure 8 ID = 1.5A, VGS = -2.5V Figure 8 THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.14 in2 (90.3 mm2) (Note 2) Pad Area = 0.027 in2 (17.4 mm2) Figure 20 Pad Area = 0.006 in2 (3.9 mm2) Figure 20 SWITCHING SPECIFICATIONS (VGS = -2.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(ON) tr td(OFF) tf VDD = -10V, ID = 1.5A VGS = -2.5V, RGS = 10 Figures 14, 18, 19 13 85 55 62 ns ns ns ns 50 191 228 oC/W oC/W oC/W TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS BVDSS IDSS IGSS ID = 250A, VGS = 0V Figure 11 VDS = -20V, VGS = 0V VGS = 12V -20 - - -1 10 V A uA -0.5 - 0.028 0.030 0.044 -1.5 0.037 0.039 0.059 V SWITCHING SPECIFICATIONS (VGS = -4.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at -2V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = -10V, VGS = 0V, f = 1MHz Figure 12 1200 325 130 pF pF pF Qg(TOT) Qg(-2) Qg(TH) Qgs Qgd VGS = 0V to -4.5V VGS = 0V to -2V VGS = 0V to -0.5V VDD = -10V, ID = 6.0A, Ig(REF) = 1.0mA Figures 13, 16, 17 12 6 0.7 2.5 3.5 nC nC nC nC nC td(ON) tr td(OFF) tf VDD = -10V, ID = 6.0A VGS = -4.5V, RGS = 10 Figures 15, 18, 19 9 72 81 82 ns ns ns ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = -6.0A ISD = -6.0A, dISD/dt = 100A/s ISD = -6.0A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP -0.85 24 17 MAX UNITS V ns nC 2 ITF87072DK8T Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) -6 VGS = -4.5V, RJA = 50oC/W -4 0.8 0.6 0.4 0.2 0 0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) TA, AMBIENT TEMPERATURE (oC) -8 -2 VGS = -2.5V, RJA = 228oC/W FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 2 1 THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.01 SINGLE PULSE 0.001 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 102 103 RJA = 228oC/W ZJA, NORMALIZED 0.1 10-4 103 10-2 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -400 RJA = 228oC/W IDM, PEAK CURRENT (A) -100 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 VGS = -2.5V -10 VGS = -4.5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 FIGURE 4. PEAK CURRENT CAPABILITY 3 ITF87072DK8T Typical Performance Curves -200 -100 ID, DRAIN CURRENT (A) SINGLE PULSE TJ = MAX RATED TA = 25oC RJA = 228oC/W 100s (Continued) -25 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) -20 -15 -10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms -1 -1 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) -50 -10 TJ = 150oC TJ = 25oC -5 TJ = -55oC -1.5 -2.0 -2.5 -3.0 -0 -1.0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. TRANSFER CHARACTERISTICS -25 TA = 25oC 80 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -2.5V VGS = -3V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = -1.5A 60 ID = -6A ID, DRAIN CURRENT (A) -20 VGS = -4.5V -15 -10 VGS = -2V 40 -5 VGS = -1.5V 0 0 -0.5 -1.0 -1.5 -2.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 20 -1 -2 -3 -4 -5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE 1.4 1.4 VGS = VDS, ID = -250A 1.2 1.2 VGS = -4.5V, ID = -6A 1.0 1.0 0.8 0.8 0.6 0.6 -80 -40 0 40 80 120 160 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4 ITF87072DK8T Typical Performance Curves 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = -250A 1000 (Continued) 2000 CISS = CGS + CGD 1.1 C, CAPACITANCE (pF) COSS CDS + CGD 1.0 CRSS = CGD 0.9 -80 -40 0 40 80 120 160 100 -0.1 VGS = 0V, f = 1MHz -1 VDS , DRAIN TO SOURCE VOLTAGE (V) -10 -20 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -5 VGS , GATE TO SOURCE VOLTAGE (V) VDD = -10V FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 200 -4 SWITCHING TIME (ns) 150 VGS = -2.5V, VDD = -10V, ID = -1.5A tr -3 -2 WAVEFORMS IN DESCENDING ORDER: ID = -6A ID = -1.5A 0 3 6 9 12 15 100 tf td(OFF) td(ON) -1 50 0 0 Qg, GATE CHARGE (nC) 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 14. SWITCHING TIME vs GATE RESISTANCE 200 VGS = -4.5V, VDD = -10V, ID = -6A SWITCHING TIME (ns) 150 tf 100 tr 50 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () td(OFF) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE 5 ITF87072DK8T Test Circuits and Waveforms Qgs RL 0 VGS= -0.5V VGS VDD + VDS Qgd VDS Qg(TH) -VGS Qg(-2) VDD Qg(TOT) 0 Ig(REF) VGS= -2V DUT Ig(REF) VGS= -4.5V FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS tON td(ON) RL VDS VGS + tOFF td(OFF) tr tf 10% 10% 0 0V RGS -VGS DUT 0 VDS 90% 90% 10% 50% VGS PULSE WIDTH 90% 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM 6 ITF87072DK8T Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM - T A ) P DM = -----------------------------R JA 300 RJA = 103.2 - 24.3 250 * ln(AREA) 228 oC/W - 0.006in2 191 oC/W - 0.027in2 R, RJA (oC/W) 200 150 100 50 (EQ. 1) R = 46.4 - 21.7 * ln(AREA) 0 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) PER DIE In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R JA = 103.2 - 24.3 x FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA While Equation 2 describes the thermal resistance of a single die, several devices are offered with two die in the SO8 package. The dual die SO8 package introduces an additional thermal component, thermal coupling resistance, R. Equation 3 describes R as a function of the top copper mounting pad area. R = 46.4 - 21.7 x ln ( Area ) (EQ. 3) The thermal coupling resistance vs copper area is also graphically depicted in Figure 20. It is important to note the thermal resistance (RJA) and thermal coupling resistance (R) are equivalent for both die. For example at 0.1 square inches of copper: RJA1 = RJA2 = 159oC/W R1 = R2 = 97oC/W TJ1 and TJ2 define the junction temperature of the respective die. Similarly, P1 and P2 define the power dissipated in each die. The steady state junction temperature can be calculated using Equation 4 for die 1 and Equation 5 for die 2. Example: To calculate the junction temperature of each die when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0 Watts. The ambient temperature is 70oC and the package is mounted to a top copper area of 0.1 square inches per die. Use Equation 4 to calculate TJ1 and Equation 5 to calculate TJ2. . T J1 = P 1 R JA + P 2 R + T A (EQ. 4) TJ1 = (0 Watts)(159C/W) + (0.5 Watts)(97C/W) + 70C TJ1 = 119C T J2 = P 2 R JA + P 1 R + T A (EQ. 5) ln ( Area ) (EQ. 2) TJ2 = (0.5 Watts)(159C/W) + (0 Watts)(97C/W) + 70C TJ2 = 150C 7 ITF87072DK8T The transient thermal impedance (ZJA) is also affected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 160 IMPEDANCE (oC/W) ZJA, THERMAL 120 COPPER BOARD AREA - DESCENDING ORDER 0.020 in2 0.140 in2 0.257 in2 0.380 in2 0.493 in2 80 40 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 21. THERMAL RESISTANCE vs MOUNTING PAD AREA 8 ITF87072DK8T PSPICE Electrical Model .SUBCKT ITF87072DK8 2 1 3 ; CA 12 8 1.15e-9 CB 15 14 1.2e-9 CIN 6 8 1.09e-9 ESG LDRAIN + 5 RLDRAIN EBREAK ESLC 50 DBODY + 17 18 DRAIN 2 RSLC1 51 REV Dec 1999 RSLC2 DPLCAP EVTHRES + 19 8 6 LGATE EVTEMP RGATE 9 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 3.6e-9 LSOURCE 3 7 4.3e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD GATE 1 RLGATE - 20 DESD1 91 DESD2 18 + 22 CIN RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5.8e-3 RGATE 9 20 16.1 RLDRAIN 2 5 10 RLGATE 1 9 36 RLSOURCE 3 7 43 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.1e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),2.1))} .MODEL DBODYMOD D (IS = 1.7e-10 IKF = 3 N = 1.18 RS = 1.05e-2 TRS1 = 1.75e-3 TRS2 = 5.08e-6 CJO = 6e-10 TT = 5.1e-9 M = 0.47) .MODEL DBREAKMOD D (RS = 4e-1 TRS1 = 1e-3 TRS2 = -2e-5) .MODEL DESD1MOD D (BV = 9.5 TBV1 = -2.9e-3 N = 12 RS = 35) .MODEL DESD2MOD D (BV = 10.2 TBV1 = -2.5e-3 N = 13 RS = 35) .MODEL DPLCAPMOD D (CJO = 4.7e-10 IS = 1e-30 N = 10 M = 0.4 VJ = 0.45) .MODEL MMEDMOD PMOS (VTO = -1.15 KP = 23 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 16.1 RS = 0.1) .MODEL MSTROMOD PMOS (VTO = -1.35 KP = 30 LAMBDA = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD PMOS (VTO = -0.82 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 161 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9e-4 TC2 = 1e-6) .MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 1.2e-6) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 5e-6) .MODEL RVTHRESMOD RES (TC1 = 1.3e-3 TC2 = 2.3e-6) .MODEL RVTEMPMOD RES (TC1 = -4e-4 TC2 = -1e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 2.5 VOFF= 1.5) VON = 1.5 VOFF= 2.5) VON = 0.75 VOFF= -0.5) VON = -0.5 VOFF= 0.75) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 9 - EBREAK 5 11 17 18 -29.6 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 5 51 + DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 6 DPLCAPMOD 10 - 8 6 - RDRAIN 21 16 MWEAK MMED MSTRO 8 RSOURCE DBREAK 11 LSOURCE 7 RLSOURCE SOURCE 3 RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES ITF87072DK8T SABER Electrical Model REV Dec 1999 template itf87072dk8 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 1.7e-10, ikf = 3, nl = 1.18, cjo = 6e-10, tt = 5.1e-9, m = 0.47, rs = 1.05e-2, trs1 = 1.75e-3, trs2 = 5.08e-6) dp..model dbreakmod = (rs = 4e-1, trs1 = 1e-3, trs2 = -2e-5) dp..model desd1mod = (bv = 9.5, tbv1 = -2.9e-3, nl = 12, rs = 35) dp..model desd2mod = (bv = 10.2, tb1 = -2.5e-3, nl = 13, rs = 35) dp..model dplcapmod = (cjo = 4.7e-10, isl = 10e-30, nl = 10, m = 0.4, vj = 0.45) m..model mmedmod = (type=_p, vto = -1.15, kp = 23, is = 1e-30, tox = 1, rs = 0.1) m..model mstrongmod = (type=_p, vto = -1.35, kp = 30, lambda = 0.05, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.82, kp = 0.06, is = 1e-30, tox = 1, rs = 0.1) LDRAIN ESG sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5) 5 -8+ sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5) 6 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.75, voff = -0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.75) RLDRAIN + 10 c.ca n12 n8 = 1.15e-9 c.cb n15 n14 = 1.2e-9 c.cin n6 n8 = 1.09e-9 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod dp.dplcap n10 n6 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 3.6e-9 l.lsource n3 n7 = 4.3e-9 GATE 1 RLGATE 91 DESD2 DPLCAP EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A S2A RBREAK 13 8 S1B 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 14 IT 15 17 18 RVTEMP 19 7 SOURCE 3 RSLC1 51 RSLC2 ISCL 50 RDRAIN 16 21 MWEAK MMED DBODY DBREAK EBREAK 17 18 DRAIN 2 - 11 LGATE RGATE 9 EVTEMP - 20 DESD1 18 + 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9e-4, tc2 = 1e-6 res.rdrain n50 n16 = 5.8e-3, tc1 = 1.2e-2, tc2 = 1.2e-6 res.rgate n9 n20 = 16.1 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 36 res.rlsource n3 n7 = 43 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.1e-2, tc1 = 0, tc2 = 5e-6 res.rvtemp n18 n19 = 1, tc1 = -4e-4, tc2 = -1e-7 res.rvthres n22 n8 = 1, tc1 = 1.3e-3, tc2 = 2.3e-6 spe.ebreak n5 n11 n17 n18 = -29.6 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n8 n6 = 1 spe.evtemp n6 n20 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 12 CA VBAT + - - 8 RVTHRES 22 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/100))** 2.1)) } } 10 ITF87072DK8T SPICE Thermal Model REV April 1999 ITF87072DK8 Copper Area = 0.02 in2 CTHERM1 th 8 8.5e-4 CTHERM2 8 7 1.8e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 1.3e-2 CTHERM5 5 4 4.0e-2 CTHERM6 4 3 9.0e-2 CTHERM7 3 2 4.0e-1 CTHERM8 2 tl 1.4 RTHERM1 th 8 3.5e-2 RTHERM2 8 7 6.0e-1 RTHERM3 7 6 2 RTHERM4 6 5 8 RTHERM5 5 4 18 RTHERM6 4 3 39 RTHERM7 3 2 42 RTHERM8 2 tl 48 th JUNCTION RTHERM1 8 CTHERM1 RTHERM2 7 CTHERM2 RTHERM3 6 CTHERM3 RTHERM4 5 CTHERM4 SABER Thermal Model Copper Area = 0.02 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 8.5e-4 ctherm.ctherm2 8 7 = 1.8e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 1.3e-2 ctherm.ctherm5 5 4 = 4.0e-2 ctherm.ctherm6 4 3 = 9.0e-2 ctherm.ctherm7 3 2 = 4.0e-1 ctherm.ctherm8 2 tl = 1.4 rtherm.rtherm1 th 8 = 3.5e-2 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 2 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 18 rtherm.rtherm6 4 3 = 39 rtherm.rtherm7 3 2 = 42 rtherm.rtherm8 2 tl = 48 } RTHERM5 CTHERM5 4 RTHERM6 3 CTHERM6 RTHERM7 2 CTHERM7 RTHERM8 CTHERM8 tl AMBIENT TABLE 1. THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 9.0e-2 4.0e-1 1.4 39 42 48 0.14 in2 1.3e-1 6.0e-1 2.5 26 32 35 0.257 in2 1.5e-1 4.5e-1 2.2 20 31 38 0.38 in2 1.5e-1 6.5e-1 3 20 29 31 0.493 in2 1.5e-1 7.5e-1 3 20 23 25 11 ITF87072DK8T MS-012AA 8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE E E1 1 e 2 A A1 INCHES SYMBOL A A1 b c MIN 0.0532 0.004 0.013 0.0075 0.189 0.2284 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.244 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 NOTES 2 3 4 D 6 D b E E1 e H 5 h x 45o 0.050 BSC 0.0099 0.016 0.0196 0.050 1.27 BSC 0.25 0.40 0.50 1.27 c L L 0.060 1.52 0o-8o 0.004 IN 0.10 mm 0.050 1.27 0.024 0.6 0.155 4.0 0.275 7.0 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE-MOUNTED APPLICATIONS NOTES: 1. All dimensions are within allowable dimensions of Rev. C of JEDEC MS-012AA outline dated 5-90. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. "L" is the length of terminal for soldering. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Controlling dimension: Millimeter. 7. Revision 8 dated 5-99. 1.5mm DIA. HOLE 4.0mm USER DIRECTION OF FEED 2.0mm 1.75mm C L MS-012AA 12mm TAPE AND REEL 12mm 8.0mm 40mm MIN. ACCESS HOLE 18.4mm COVER TAPE 13mm 330mm 50mm GENERAL INFORMATION 1. 2500 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 12.4mm 12 ITF87072DK8T All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 13 |
Price & Availability of ITF87072DK8T
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |